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Agilent HCPL-7710, HCPL-0710 40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Description Available in either an 8-pin DIP or SO-8 package style respectively, the HCPL-7710 or HCPL-0710 optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-x710 require only two bypass capacitors for complete CMOS compatibility.
Basic building blocks of the HCPL-x710 are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver.
Functional Diagram
TRUTH TABLE (POSITIVE LOGIC) VI, INPUT VI 2 IO * 3 LED1 GND1 4 SHIELD 5 GND2 6 VO 7 NC* H L LED1 OFF ON VO, OUTPUT H L
Features * +5 V CMOS compatibility * 8 ns maximum pulse width distortion * 20 ns maximum prop. delay skew * High speed: 12 Mbd * 40 ns maximum prop. delay * 10 kV/s minimum common mode rejection * -40C to 100C temperature range * Safety and regulatory approvals UL Recognized 3750 V rms for 1 min. per UL 1577 CSA Component Acceptance Notice #5 IEC/EN/DIN EN 60747-5-2 - VIORM = 630 Vpeak for HCPL-7710 Option 060 - VIORM = 560 Vpeak for HCPL-0710 Option 060 Applications * Digital fieldbus isolation: DeviceNet, SDS, Profibus * AC plasma display panel level shifting * Multiplexed data transmission * Computer peripheral interface * Microprocessor system interface
**VDD1
1
8
VDD2**
* Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin 7 is not connected internally. ** A 0.1 F bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide 8-Pin DIP (300 Mil) HCPL-7710
Small Outline SO-8 HCPL-0710
Ordering Information Specify Part Number followed by Option Number (if desired) Example HCPL-7710#XXXX 060 = IEC/EN/DIN EN 60747-5-2 Option. 300 = Gull Wing Surface Mount Option (HCPL-7710 only). 500 = Tape and Reel Packaging Option. XXXE = Lead Free Option No Option and Option 300 contain 50 units (HCPL-7710), 100 units (HCPL-0710) per tube. Option 500 contain 1000 units (HCPL-7710), 1500 units (HCPL-0710) per reel. Option data sheets available. Contact Agilent sales representative or authorized distributor.
Remarks: The notation "#" is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use "-"
Package Outline Drawing HCPL-7710 8-Pin DIP Package
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 OPTION 060 CODE*
7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) DATE CODE
A XXXXV YYWW 1 1.19 (0.047) MAX. 2 3 4
1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
5 TYP. 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
1.080 0.320 (0.043 0.013)
0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010)
2
Package Outline Drawing HCPL-7710 Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010)
8 7 6 5
1.016 (0.040)
6.350 0.25 (0.250 0.010)
10.9 (0.430)
1
2
3
4
1.27 (0.050)
2.0 (0.080)
1.19 (0.047) MAX.
1.780 (0.070) MAX.
9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
3.56 0.13 (0.140 0.005)
1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 0.25 (0.025 0.010)
12 NOM.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Package Outline Drawing HCPL-0710 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
7
6
5
3.937 0.127 (0.155 0.005)
XXXV YWW
5.994 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) DATE CODE
4
7.49 (0.295)
PIN ONE 1 0.406 0.076 (0.016 0.003)
2
3
1.9 (0.075)
1.270 BSC (0.050)
0.64 (0.025)
* 5.080 0.127 (0.200 0.005)
7
45 X
0.432 (0.017)
3.175 0.127 (0.125 0.005)
0 ~ 7 1.524 (0.060) 0.203 0.102 (0.008 0.004)
0.228 0.025 (0.009 0.001)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. OPTION NUMBER 500 NOT MARKED.
0.305 MIN. (0.012)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3
Solder Reflow Thermal Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
Regulatory Information The HCPL-x710 have been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. (Option 060 only)
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Recommended Pb-Free IR Profile
tp Tp TL TEMPERATURE Tsmax Tsmin ts PREHEAT 60 to 180 SEC. 25 t 25 C to PEAK TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C tL 60 to 150 SEC. 260 +0/-5 C 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C RAMP-DOWN 6 C/SEC. MAX. TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC.
Insulation and Safety Related Specifications Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Symbol L(I01) L(I02) 7710 7.1 7.4 Value 0710 4.9 4.8 Units mm mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1
0.08 175
0.08 175
mm
Volts
IIIa
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1) There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit 4
board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060) Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 V rms for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11.) Case Temperature Input Current Output Power Insulation Resistance at TS, V10 = 500 V Symbol HCPL-7710 Option 060 I-IV I-IV I-III 55/100/21 2 630 1181 HCPL-0710 Option 060 I-IV I-III 55/100/21 2 560 1050 Units
VIORM VPR
V peak V peak
VPR
945
840
V peak
VIOTM
6000
4000
V peak
TS IS,INPUT PS,OUTPUT RIO
175 230 600 109
150 150 600 109
C mA mW
Refer to the front of the optocoupler section of the Isolation and Control Component Designer's Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description. Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Note: The surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature Supply Voltages Input Voltage Output Voltage Input Current Average Output Current Lead Solder Temperature Solder Reflow Temperature Profile Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times 5
Symbol TS TA VDD1, VDD2 VI VO II IO
Max. Units 125 C +100 C 6.0 Volts VDD1 +0.5 Volts VDD2 +0.5 Volts +10 mA 10 mA 260C for 10 sec., 1.6 mm below seating plane See Solder Reflow Temperature Profile Section
Min. -55 -40 0 -0.5 -0.5 -10
Figure
Symbol TA VDD1, VDD2 VIH VIL tr , t f
Min. -40 4.5 2.0 0.0
Max. +100 5.5 VDD1 0.8 1.0
Units C V V V ms
Figure
1, 2
Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25C, VDD1 = VDD2 = +5 V. Parameter DC Specifications Logic Low Input Supply Current Logic High Input Supply Current Input Supply Current Output Supply Current Input Current Logic High Output Voltage Logic Low Output Voltage Switching Specifications Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output Pulse Width Data Rate Pulse Width Distortion |tPHL - tPLH| Propagation Delay Skew Output Rise Time (10 - 90%) Output Fall Time (90 - 10%) Common Mode Transient Immunity at Logic High Output Common Mode Transient Immunity at Logic Low Output Input Dynamic Power Dissipation Capacitance Output Dynamic Power Dissipation Capacitance Symbol IDD1L IDD1H IDD1 IDD2 II VOH VOL Min. Typ. 6.0 1.5 Max. Units 10.0 3.0 13.0 11.0 10 mA mA mA mA A V V Test Conditions VI = 0 V VI = VDDI Fig. Note 1
5.5 -10 4.4 4.0 5.0 4.8 0 0.5 20 23 80 3
0.1 1.0 40 40
IO = -20 A, VI = VIH IO = -4 mA, VI = VIH IO = 20 A, VI = VIL IO = 4 mA, VI = VIL CL = 15 pF CMOS Signal Levels
1, 2
tPHL tPLH PW PWD tPSK tR tF |CMH| 10
ns
3, 7
2
3 12.5 8 20 9 8 20 kV/s VI = VDD1 , VO > 0.8 VDD1 , VCM = 1000 V VI = 0 V, VO > 0.8 V, VCM = 1000 V 5, 9 6, 10 6 MBd ns 4, 8 4 5
|CML|
10
20
CPD1
60
pF
7
CPD2
10
6
Package Characteristics Parameter Input-Output Momentary Withstand Voltage Resistance (Input-Output) Capacitance (Input-Output) Input Capacitance Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Package Power Dissipation 0710 7710 Symbol VISO Min. 3750 3750 Typ. Max. Units Vrms Test Conditions RH 50%, t = 1 min., TA = 25C VI-O = 500 Vdc f = 1 MHz 11 C/W Thermocouple located at center underside of package Fig. Note 8, 9, 10 8
RI-O CI-O CI jci jco PPD
1012 0.6 3.0 145 160 140 135 150
pF
-7710 -0710 -7710 -0710
mW
9. In accordance with UL1577, each HCPL0710 is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, II-O 5 A). Each HCPL-7710 is proof tested by applying an insulation test voltage 4500 V rms for 1 second (leakage detection current limit, II-O 5 A). 10. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." 11. CI is the capacitance measured at pin 2 (VI).
Notes: 1. The LED is ON when VI is low and OFF when VI is high. 2. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 3. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaranteed. Maximum Data Rate is the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is 30%, the maximum data rate becomes 37.5 MBd. Please note that HCPL-x710 performances above 12.5 MBd are not guaranteed by Hewlett-Packard.
4. PWD is defined as |t PHL - tPLH |. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 6. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CM L is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD , where f is switching frequency in MHz. 8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
2.2
5 4
VO (V)
2.0
VITH (V)
TPLH, TPHL (ns)
0 C 25 C 85 C
2.1
0 C 25 C 85 C
29 27 25 23 21 19 17 TPHL TPLH
3 2 1 0
1.9 1.8 1.7 1.6 4.5
0
1
2 VI (V)
3
4
5
4.75
5 VDD1 (V)
5.25
5.5
15
0
10
20 30
40
50
60 70
80
TA (C)
Figure 1. Typical output voltage vs. input voltage.
Figure 2. Typical input voltage switching threshold vs. input supply voltage.
Figure 3. Typical propagation delays vs. temperature.
7
4
11
7
3
6
10
PWD (ns) TR (ns)
2
TF (ns)
5
4
9
1
3
0
0
20
40 TA (C)
60
80
8
0
20
40 TA (C)
60
80
2
0
20
40 TA (C)
60
80
Figure 4. Typical pulse width distortion vs. temperature.
Figure 5. Typical rise time vs. temperature.
Figure 6. Typical fall time vs. temperature.
29 27 TPLH, TPHL (ns) 25 23 21 TPLH 19 17 15 15 20 25 30 35 40 45 50
6 5 4
PWD (ns)
TR (ns)
TPHL
21 19 17 15 13 11 9 7 5 3
3 2 1 0 15
20
25
30
35
40
45
50
1
0
5
10
15
20
25
30
35
CI (pF)
CI (pF)
CI (pF)
Figure 7. Typical propagation delays vs. output load capacitance.
Figure 8. Typical pulse width distortion vs. output load capacitance.
Figure 9. Typical rise time vs. load capacitance.
OUTPUT POWER - PS, INPUT CURRENT - IS
OUTPUT POWER - PS, INPUT CURRENT - IS
10 9 8
FALL TIME (ns)
800 700 600 500 400 300 (230) 200 100 0 0
STANDARD 8 PIN DIP PRODUCT PS (mW) IS (mA)
800 700 600 500 400 300 200 (150) 100 0 0
SURFACE MOUNT SO8 PRODUCT PS (mW) IS (mA)
7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35
25
50
75 100 125 150 175 200
25
50
75 100 125 150 175 200
CI (pF)
TA - CASE TEMPERATURE - C
TA - CASE TEMPERATURE - C
Figure 10. Typical fall time vs. load capacitance.
Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per IEC/EN/DIN EN 60747-5-2.
8
Application Information Bypassing and PC Board Layout The HCPL-x710 optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-x710 use highspeed CMOS IC technology allowing CMOS logic to be
connected directly to the inputs and outputs. As shown in Figure 12, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.01 F and
0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 13 illustrates the recommended printed circuit board layout for the HPCL-x710.
VDD1 C1 VI
1 2 NC 3 GND1 4
8 C2 7 NC 6 5 GND2
710 YWW
VDD2
VO
C1, C2 = 0.01 F TO 0.1 F
Figure 12. Recommended Printed Circuit Board layout.
VDD1 VI
C1
VDD2
710 YWW
C2
VO GND1 GND2 C1, C2 = 0.01 F TO 0.1 F
Figure 13. Recommended Printed Circuit Board layout.
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga-
tion delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the
amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure 14.
INPUT VI tPLH OUTPUT VO 90% 10% tPHL 90%
5 V CMOS 50% 0V
10%
VOH 2.5 V CMOS VOL
Figure 14.
9
Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable. The PWD specification for the HCPL-x710 is 8 ns (10%) maximum across recommended operating conditions. 10% maximum is dictated by the most stringent of the three fieldbus standards, PROFIBUS. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals
on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating
temperature). As illustrated in Figure 15, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 16 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock.
VI
50%
INPUTS
DATA
VO
2.5 V, CMOS tPSK
CLOCK
VI
50%
DATA OUTPUTS tPSK
VO
2.5 V, CMOS
CLOCK tPSK
Figure 15. Propagation delay skew waveform.
Figure 16. Parallel data transmission example.
Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or 10
some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a problem. The HCPL-x710 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges.
Digital Field Bus Communication Networks To date, despite its many drawbacks, the 4 - 20 mA analog current loop has been the most widely accepted standard for implementing process control systems. In today's manufacturing environment, however, automated systems are expected to help manage the process, not merely
CONTROLLER
monitor it. With the advent of digital field bus communication networks such as DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information. Controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information.
The physical model for each of these digital field bus communication networks is very similar as shown in Figure 17. Each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices.
BUS INTERFACE OPTICAL ISOLATION TRANSCEIVER FIELD BUS TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE
XXXXXX
SENSOR
YYY
DEVICE CONFIGURATION MOTOR STARTER
MOTOR CONTROLLER
Figure 17. Typical field bus communication physical model.
Optical Isolation for Field Bus Networks To recognize the full benefits of these networks, each recommends providing galvanic isolation using Agilent optocouplers. Since network communication is bidirectional (involving receiving data from and transmitting data onto the network), two Agilent optocouplers are needed. By providing galvanic isolation, data integrity is retained via noise reduction and the elimination of false signals. In addition, the 11
network receives maximum protection from power system faults and ground loops. Within an isolated node, such as the DeviceNet Node shown in Figure 18, some of the node's components are referenced to a ground other than V- of the network. These components could include such things as devices with serial ports, parallel ports, RS232 and RS485 type ports. As shown in Figure 18, power from the network is used only for the
transceiver and input (network) side of the optocouplers. Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-x710 optocouplers. For each network, the HCPL-x710 satisify the critical propagation delay and pulse width distortion requirements over the temperature range of 0C to +85C, and power supply voltage range of 4.5 V to 5.5 V.
AC LINE
NODE/APP SPECIFIC uP/CAN
LOCAL NODE SUPPLY
HCPL x710
HCPL x710 5 V REG.
GALVANIC ISOLATION BOUNDARY
TRANSCEIVER
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
NETWORK POWER SUPPLY
Figure 18. Typical DeviceNet node.
Implementing DeviceNet and SDS with the HCPL-x710 With transmission rates up to 1 Mbit/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol -- the Controller Area Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node Powered by the Network (Figure 19),
Isolated Node with Transceiver Powered by the Network (Figure 20), and Isolated Node Providing Power to the Network (Figure 21). Isolated Node Powered by the Network This type of node is very flexible and as can be seen in Figure 19, is regarded as "isolated" because not all of its components have the same ground reference. Yet, all
components are still powered by the network. This node contains two regulators: one is isolated and powers the CAN controller, nodespecific application and isolated (node) side of the two optocouplers while the other is nonisolated. The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers.
NODE/APP SPECIFIC uP/CAN ISOLATED SWITCHING POWER SUPPLY REG. TRANSCEIVER GALVANIC ISOLATION BOUNDARY
HCPL x710
HCPL x710
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
NETWORK POWER SUPPLY
Figure 19. Isolated node powered by the network.
12
Isolated Node with Transceiver Powered by the Network Figure 20 shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network. More importantly, the unique "dual-inverting" design of the HCPL-x710 ensure the network will not "lock-up" if either AC line
power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-x710 located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-x710 output voltage (VO) go HIGH. *Bus V+ Sensing It is suggested that the Bus V+ sense block shown in Figure 20 be implemented. A locally powered node with an un-powered isolated Physical Layer will accumulate errors and become bus-off if it attempts to transmit. The Bus V+ sense signal would be used to change the BOI attribute of the
DeviceNet Object to the "autoreset" (01) value. Refer to Volume 1, Section 5.5.3. This would cause the node to continually reset until bus power was detected. Once power was detected, the BOI attribute would be returned to the "hold in bus-off" (00) value. The BOI attribute should not be left in the "auto-reset" (01) value since this defeats the jabber protection capability of the CAN error confinement. Any inexpensive low frequency optical isolator can be used to implement this feature.
AC LINE
NODE/APP SPECIFIC uP/CAN
NON ISO 5V
HCPL x710
HCPL x710
*HCPL x710
GALVANIC ISOLATION BOUNDARY
REG. TRANSCEIVER
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
NETWORK POWER SUPPLY
* OPTIONAL FOR BUS V + SENSE
Figure 20. Isolated node with transceiver powered by the network.
13
Isolated Node Providing Power to the Network Figure 21 shows a node providing power to the network. The AC line powers a regulator which provides five (5) volts locally. The AC line also powers a 24 volt isolated supply, which powers the network, and another five-volt regulator, which, in turn, powers the transceiver and isolated
(network) side of the two optocouplers. This method is recommended when there are a limited number of devices on the network that don't require much power, thus eliminating the need for separate power supplies. More importantly, the unique "dual-inverting" design of the HCPL-x710 ensure the network
will not "lock-up" if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-x710 located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-x710 output voltage (VO) go HIGH.
AC LINE
DEVICENET NODE NODE/APP SPECIFIC uP/CAN ISOLATED SWITCHING POWER SUPPLY 5 V REG. TRANSCEIVER GALVANIC ISOLATION BOUNDARY 5 V REG.
HCPL x710
HCPL x710
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
Figure 21. Isolated node providing power to the network.
14
Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure 22. Since the HCPL-x710 are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the CAN
GALVANIC ISOLATION BOUNDARY
transceiver. Two bypass capacitors (with values between 0.01 and 0.1 F) are required and should be located as close as possible to the input and output power-supply pins of the HCPLx710. For each capacitor, the total
lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the highspeed digital nature of the signals inside the optocoupler.
ISO 5 V
5V 1 VDD1 VDD2 8 7 0.01 F TxD VCC CANH + + LINEAR OR SWITCHING REGULATOR + 5 V+ 4 CAN+ 3 SHIELD CANL Rs 5 GND2 GND1 4 3 0.01 F GND REF RXD D1 30 V C1 0.01 F 500 V R1 1M VREF 2 CAN- 1 V-
TX0
2 VIN
HCPL-x710
0.01 F 3 4 GND1 GND VO 6 GND2 5
82C250
C4 0.01 F
RX0
6 VO
HCPL-x710
0.01 F 7 8 VDD2 ISO 5 V VIN 2 VDD1 1 5V
Figure 22. Recommended DeviceNet application circuit.
Implementing PROFIBUS with the HCPL-x710 An acronym for Process Fieldbus, PROFIBUS is essentially a twisted-pair serial link very similar to RS-485 capable of achieving high-speed communication up to 12 MBd. As shown in Figure 23, a PROFIBUS Controller (PBC) establishes the connection of a field automation unit (control or central processing station) or a field device to the transmission medium. The PBC consists of the line transceiver, optical isolation, frame character transmitter/ receiver (UART), and the FDL/ APP processor with the interface to the PROFIBUS user. 15
PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE
USER INTERFACE FDL/APP PROCESSOR UART PBC OPTICAL ISOLATION
TRANSCEIVER MEDIUM
Figure 23. PROFIBUS Controller (PBC).
Power Supplies and Bypassing The recommended PROFIBUS application circuit is shown in Figure 24. Since the HCPL-x710 are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 and 0.1 F) are required and should be located as close as possible to the input and output power-supply pins of the HCPL-x710. For each capacitor,
the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. Being very similar to multi-station RS485 systems, the HCPL-061N optocoupler provides a transmit disable function which is necessary to make the bus free
after each master/slave transmission cycle. Specifically, the HCPL-061N disables the transmitter of the line driver by putting it into a high state mode. In addition, the HCPL-061N switches the RX/TX driver IC into the listen mode. The HCPL-061N offers HCMOS compatibility and the high CMR performance (1 kV/s at VCM = 1000 V) essential in industrial communication interfaces.
GALVANIC ISOLATION BOUNDARY
5V 8 VDD2 0.01 F Rx 7 VDD1 1 VIN 2 ISO 5 V ISO 5 V
HCPL-x710
6 VO 5 GND2 3 GND1 4
0.01 F 0.01 F
1
R
8 VCC A6 + RT B 7 SHIELD -
SN75176B
4 3 D DE GND 5
5V 1 VDD1 Tx 2 VIN VDD2 8 7
ISO 5 V
2 RE 0.01 F
0.01 F
1M
HCPL-x710
0.01 F 3 4 GND1 VO 6 GND2 5
ISO 5 V 1 5V 2 ANODE Tx ENABLE 1, 0 k 3 CATHODE 4 VE 7 0.01 F VO 6 GND 5 680 VCC 8
HCPL-061N
Figure 24. Recommended PROFIBUS application circuit.
16
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152 (Domestic/International), or 0120-61-1280 (Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2005 Agilent Technologies, Inc. Obsoletes 5989-0789EN February 28, 2005 5989-2134EN

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